The ICS95V847 is a low skew, low jitter PLL clock driver that provides 1 to 5 differential clock distribution with feedback pins for input to output synchronization. It is suitable for zero delay board fan out and SO-DIMM applications, providing a complete DDR registered DIMM solution.
The ICS95V847 is a zero delay buffer designed to distribute a differential clock input pair to five differential pairs of clock outputs and one feedback output. It operates as a PLL clock driver, utilizing input and feedback clocks to provide high-performance, low-skew, and low-jitter differential output clocks suitable for DDR registered DIMM solutions.
The device is characterized for operation with a supply voltage (VDD) and analog power supply (AVDD) of 2.5V. It supports an application frequency range from 45 MHz to 233 MHz and tracks Spread Spectrum Clocking (SSC) to reduce EMI. The component is available in a 24-pin TSSOP package with dimensions of 4.40 mm body and 0.65 mm pitch.
| Supply Voltage (VDD & AVDD) | 2.5 V +/- 0.2V |
|---|---|
| Operating Temperature Range | 0°C to +85°C |
| Output to Output Skew | <60ps |
It distributes a differential clock input pair to five differential pairs of clock outputs.
Yes, it is able to track Spread Spectrum Clock (SSC) for reduced EMI.