This document introduces the TMS320C1x series of digital signal processors, including performance, memory, peripherals, and packaging.
The TMS320C1x family is a series of 16‑bit digital signal processors that combine high‑speed controller flexibility with array‑processor numerical capability. All devices are object‑code compatible with the original TMS32010 and offer up to 8.77 MIPS performance.
The datasheet provides a quick reference table of device parameters, package options, and detailed sections on architecture, instruction set, memory organization, I/O, serial ports, companding hardware, and coprocessor interfaces. It also lists specifications such as on‑chip RAM/ROM sizes, cycle times, and external memory expansion capabilities.
| Maximum processing speed | 8.77 MIPS |
|---|---|
| On‑chip data RAM | 144‑word or 256‑word |
| On‑chip program ROM | 1.5K‑ to 8K‑word |
| On‑chip program EPROM (optional) | 4K‑word |
| Cycle time options | 160 ns, 200 ns, 280 ns |
| ALU/Accumulator width | 32‑bit |
| Parallel multiplier | 16 × 16‑bit with 32‑bit product |
| External program memory support | Up to 64K‑word (except C17/E17/LC17/P17) |
The devices can achieve up to 8.77 MIPS.
They provide 144‑ or 256‑word data RAM, 1.5K‑ to 8K‑word program ROM, and an optional 4K‑word EPROM.
All devices except the C17/E17/LC17/P17 versions can execute from off‑chip external memory up to 64 K‑words.
Versions are available with 160 ns, 200 ns, or 280 ns cycle times.