Dallas Semiconductor DS1003 Silicon Delay Line Datasheet


Dallas Semiconductor DS1003 Silicon Delay Line Datasheet - cover page
Brand
Dallas Semiconductor
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
8
File format
PDF
File size
321 KB
Published
11 May, 2012
Updated
21 June, 2012
MD5 checksum
0C18498D42E1F365550E61BAF06538FC

About this manual

The DS1003 is an all‑silicon 4‑tap delay line designed for RISC microprocessors and coprocessors. It delivers four delayed clock phases, preserves input symmetry, and offers TTL/CMOS‑compatible inputs and outputs. The device is supplied in 8‑pin and 14‑pin DIP packages and can drive up to four LS‑TTL or CMOS loads per tap.

Typical applications include timing generation for RISC systems, where precise phase relationships are required. The datasheet details electrical characteristics, absolute maximum ratings, pin assignments, test setup, and mechanical dimensions, allowing designers to integrate the part into their circuits with confidence.

What's inside

  • Features
  • Description
  • Pin Assignment
  • Absolute Maximum Ratings
  • DC Electrical Characteristics
  • AC Electrical Characteristics
  • Typical Application
  • Test Setup Description
  • Mechanical Drawings

Specifications

Supply Voltage (Vcc)4.75 V min / 5.00 V typ / 5.25 V max
Input High Voltage (ViH)≥ 2 V
Input Low Voltage (ViL)≤ 0.8 V
Maximum Output Current (DS1003‑40)125 mA

Frequently asked questions

What package options are available for the DS1003?

The DS1003 is offered in 8‑pin and 14‑pin DIP packages.

How many taps does the DS1003 provide and what are they used for?

It provides four independent taps (TAP 1‑TAP 4) that generate four delayed clock phases for RISC processors and coprocessors.

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