This document introduces the features and characteristics of AT6000 series SRAM-based field programmable gate arrays (FPGAs), including high performance, low power consumption, programmable clock options, and independently configurable I/O.
This handbook describes the AT6000(LV) Series SRAM‑based FPGAs, covering features such as high‑performance system speeds over 100 MHz, low‑power operation, and flexible I/O configurations. It outlines the symmetrical array architecture, cell structure, clock and reset distribution networks, and I/O logic options.
The document also includes detailed technical specifications, device tables for AT6002, AT6003, AT6005, and AT6010, and ordering information with package types and voltage options. Contact details for Atmel worldwide locations are provided at the end.
| System Speed | > 100 MHz |
|---|---|
| Input Delay | 1.2 ns / 1.5 ns |
| Output Delay | 3.0 ns / 6.0 ns |
| Standby Current | 500 µA / 200 µA |
| Typical Operating Current | 15 mA – 170 mA |
| Voltage Options | 5.0 V (4.75‑5.25 V) and 3.3 V (3.0‑3.6 V) |
The series supports 5.0 V (4.75‑5.25 V) and 3.3 V (3.0‑3.6 V) operation.
The devices offer up to 204 user I/Os.
Standby current is specified as 500 µA (or 200 µA for low‑power mode).