The document describes a multichip module containing a field-programmable system-level integrated circuit (FPSLIC™) and secure configuration EEPROM memory. The product features 512 Kbits to 1 Mbit of configuration memory with security protection and in-system programming (ISP). The FPSLIC is an SRAM-based FPGA with an embedded high-performance RISC AVR® core and extensive data and instruction SRAM. It also includes a patented SRAM-based AT40K FPGA with 5,000 to 40,000 gates and FreeRAM™ feature, making it ideal for dynamically reconfigurable and low-power applications. The product utilizes a patented AVR enhanced RISC architecture with 120+ powerful instructions, most of which can be executed in a single clock cycle. It also includes a high-performance hardware multiplier for DSP-based systems and achieves close to 1 MIPS per MHz performance. The product offers up to 36 Kbytes of dynamically allocated instruction and data SRAM, as well as JTAG interface for extensive on-chip debugging support.
The AT94S Secure Series combines an AT40K SRAM‑based FPGA with an AVR 8‑bit RISC microcontroller and an AT17 configuration EEPROM. The multi‑chip module provides 5 000 to 40 000 FPGA gates, up to 36 KB of SRAM, and a range of AVR peripherals such as UARTs, timers and watchdog.
The handbook describes the device architecture, the two‑wire serial configurator interface, in‑system programming procedures, and detailed timing and bit‑format specifications needed to program the secure EEPROM and FPGA core.
| Configuration Memory Size | 1 Mbit |
|---|---|
| FPGA Gates | 5K to 40K |
| Operating Voltage | 3.0 – 3.6 V |
| AVR Core Frequency | 25 MHz |
The device operates from 3.0 V to 3.6 V.