This data sheet provides details on the features of the 21555 non-transparent PCI-to-PCI bridge, including compliance with the PCI local Bus Specification, Revision 2.2, PCI Power Management, Vital Product Data (VPD) support, CompactPCI Distributed Hot-Swap support, 3.3-V operation with 5.0-V tolerant I/O, selectable asynchronous or synchronous primary and secondary interface clocks, concurrent primary and secondary bus operation, Advanced Configuration Power Interface (ACPI) specification, PCI Bus Power Management specification, queuing of multiple transactions in either direction, 256 bytes of posted write (data and address) buffering in each direction, 256 bytes of read data buffering in each direction, four delayed transaction entries in each direction, two dedicated I2O delayed transaction entries, two sets of standard PCI Configuration registers corresponding to the primary and secondary interface; each set is accessible from either the primary or secondary interface, direct offset address translation for downstream memory and I/O transactions, hardware enable for secondary bus central functions, IEEE Standard 1149.1 boundary-scan JTAG interface, four primary interface base address configuration registers for downstream forwarding, with size and prefetchability programmable for all four address ranges, three secondary interface address configuration registers specifying local address ranges for upstream forwarding, with size and prefetchability programmable for all three address ranges.
The Intel 21555 bridge provides a gateway between a host PCI domain and a local subsystem. It features independent primary and secondary PCI clocks, separate address spaces, and address translation, allowing a local processor to manage subsystem resources while appearing as a single virtual device to the host.
The device operates at 3.3 V (5.0 V I/O tolerant), is available in 33 MHz and 66 MHz versions, and includes extensive buffering (256‑byte posted write and read buffers) and a 120‑message unit for intelligent I/O processing. It is packaged in a 304‑point 4‑layer PBGA.
| Operating voltage | 3.3 V (5.0 V tolerant) |
|---|---|
| Clock frequency options | 33 MHz and 66 MHz |
| Primary interface width | 64‑bit |
| Message unit | 120‑message unit |
| Posted write buffer size | 256 bytes per direction |
| Read data buffer size | 256 bytes per direction |
| Package type | 304‑point 4‑layer PBGA |
It operates at 3.3 V and is also tolerant of 5.0 V I/O levels.
The bridge is available in versions that run at 33 MHz or 66 MHz.