The Intel 82C288 is a 20‑pin CHMOS II bus controller designed for 80286 micro‑systems. It provides command and control signals for memory and I/O cycles, supports both MULTIBUS and non‑MULTIBUS timing, and operates in a fully static mode with a low‑power option.
The device is offered in 20‑pin PLCC and 20‑pin Cerdip packages and includes a range of control inputs (CENL, CMDLY, MB, READY) that allow flexible timing and bus arbitration. Detailed pin descriptions, command output tables, and waveform diagrams illustrate its operation across various bus cycles.
| Package Type | 20 Pin PLCC (Plastic) |
|---|---|
| Alternative Package | 20 Pin Cerdip |
| Technology | High Speed CHMOS II |
| Static Design | Fully static circuitry |
| Power Mode | Low power mode supported |
| Clock Frequency Relation | System clock is twice the internal processor clock frequency |
| Power Dissipation | Directly related to operating frequency |
| Maximum Output Current | 3 mA |
The 82C288 is offered in 20‑pin PLCC (plastic) and 20‑pin Cerdip packages.
When MB is HIGH the controller uses MULTIBUS timing; when LOW it uses non‑MULTIBUS timing.
The system clock frequency is twice the internal processor clock frequency.