This document describes the features and characteristics of Alliance Semiconductor's AS7C33256NTF32A and AS7C33256NTF36A products, including organization, fast clock to data access, asynchronous output enable control, multiple chip enables, and various operating modes.
The AS7C33256NTF32A/36A family is an 8‑Mb CMOS synchronous SRAM organized as 262,144 words × 32 or 36 bits. It features No Turnaround Delay (NTD) flow‑through operation, fast clock‑to‑data access (7.5/8.5/10 ns), low standby power (30 mW) and multiple chip‑enable expansion.
The devices are supplied in a 100‑pin TQFP package (14 × 20 mm) and support 3.3 V or 2.5 V I/O supplies. The datasheet provides full electrical characteristics, pin assignments, timing tables, absolute maximum ratings, and ordering information.
| Organization | 262,144 words × 32 or 36 bits |
|---|---|
| Core supply voltage | 3.3 V |
| Access time | 7.5/8.5/10 ns |
| Standby power | 30 mW typical |
| Package | 100‑pin TQFP 14 × 20 mm |
The devices operate with a 3.3 V core supply (VDD = 3.3 V + 0.165 V).
The minimum cycle times are 7.5 ns, 8.5 ns, or 10 ns depending on the speed grade.
They are offered in a 100‑pin TQFP package measuring 14 × 20 mm.
NTD stands for No Turnaround Delay, an architecture that eliminates dead bus cycles during read‑write operations.