Alliance Semiconductor AS7C31026B SRAM Datasheet

AS7C31026B 3.3 V 64K X 16 CMOS SRAM is a 6 T 0.18 u CMOS technology memory with industrial and commercial versions, center power and ground pins, high speed, low power consumption, TTL compatible, three-state I/O.


Alliance Semiconductor AS7C31026B SRAM Datasheet - cover page
Brand
Alliance Semiconductor
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
10
File format
PDF
File size
123 KB
Published
07 May, 2012
Updated
30 September, 2023
MD5 checksum
8D46C9C2C2C7711E40563DDC3FCB8F3B

About this manual

The AS7C31026B is a high‑performance 1 Mbit CMOS static RAM organized as 65,536 words × 16 bits. It offers fast address access times (10‑20 ns) and low power consumption (288 mW active, 18 mW standby) with TTL‑compatible I/O and multiple power/ground pins for low noise operation.

The document lists recommended operating conditions (3.0‑3.6 V supply, commercial temperature up to 70 °C, industrial up to 85 °C), absolute maximum ratings, timing parameters for read and write cycles, package dimensions for 44‑pin SOJ and TSOP 2, and ordering codes for commercial and industrial variants.

What's inside

  • Features
  • Functional description
  • Recommended operating conditions
  • Absolute maximum ratings
  • Read cycle timing
  • Write cycle timing
  • Package dimensions
  • Ordering codes
  • Contact information

Specifications

Memory organization65,536 words × 16 bits (1 Mbit)
Supply voltage (VCC)3.0 V min, 3.3 V nominal, 3.6 V max
Address access time10 ns – 20 ns (depending on grade)
Output enable access time5 ns – 8 ns
Active power consumption288 mW max @ 10 ns
Standby power consumption18 mW max
ESD protection2000 V
Latch‑up current200 µA
Package options44‑pin SOJ (400 mil) and 44‑pin TSOP 2

Frequently asked questions

What supply voltage range does the AS7C31026B support?

The device operates from 3.0 V to 3.6 V, with a nominal 3.3 V supply.

What are the available package types for the AS7C31026B?

It is offered in a 44‑pin SOJ (400 mil) and a 44‑pin TSOP 2 package.

What are the typical read access times for this SRAM?

Read address access times range from 10 ns to 20 ns, and output enable times from 5 ns to 8 ns.

How much power does the device consume in active mode?

Active power consumption is up to 288 mW at a 10 ns access time.

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