IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMs, using ZBTTM technology to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.
The IDT71V65602/IDT71V65802 SRAMs provide high‑speed 150 MHz operation with Zero Bus Turnaround (ZBT) technology, eliminating dead cycles between reads and writes. They feature a 4‑word burst counter, pipelined outputs, and individual byte‑write control, supporting both linear and interleaved burst sequences.
These devices are offered in JEDEC‑standard 100‑pin TQFP, 119‑ball BGA, and 165‑fine‑pitch BGA packages. They operate from a 3.3 V core supply and a 2.5 V I/O supply, with commercial temperature range 0 °C to +70 °C and industrial range –40 °C to +85 °C.
| Core Supply Voltage (VCC) | 3.135 V min / 3.3 V typ / 3.465 V max |
|---|---|
| I/O Supply Voltage (VO) | 2.375 V min / 2.5 V typ / 2.625 V max |
| Maximum Clock Frequency | 150 MHz |
| Memory Configurations | 256 K × 36 or 512 K × 18 |
| Burst Length | 4 words (interleaved or linear) |
| Commercial Operating Temperature | 0 °C to +70 °C |
| Industrial Operating Temperature | -40 °C to +85 °C |
The devices need a 3.3 V core supply (VCC) and a 2.5 V I/O supply (VO).
They are offered in two configurations: 256 K × 36 bits or 512 K × 18 bits.
The burst counter provides a four‑word burst, which can be linear or interleaved.
They support up to 150 MHz system speed.