This product is a low phase noise, phase-locked loop (PLL) 6-output clock generator with integrated 2.5 GHz VCO. It has 1 differential or 2 single-ended reference inputs, and can accept LVPECL, LVDS or CMOS reference signals, up to 250 MHz. Digital or analog lock detect can be selected. It has 3 pairs of 1.6 GHz LVPECL outputs. Each output pair shares a 1:32 divider with coarse phase delay. Additive output jitter is 225 fs rms. Channel-to-channel skew paired outputs are less than 10 ps. All outputs are automatically synchronized on power-up. Manual output synchronization is available. This product is suitable for low jitter, low phase noise clock distributors, digital baseband and wireless communication systems.
The AD9518-1 provides six LVPECL clock outputs (in three pairs) with up to 2.95 GHz frequency, an on‑chip VCO that tunes from 2.30 GHz to 2.65 GHz, and programmable dividers and phase delays. It operates from a single 3.3 V supply and supports differential, LVDS, or CMOS reference inputs up to 250 MHz.
Designed for high‑performance clock distribution, the device is suited for 10/40/100 Gb/sec networking, high‑speed ADC/DAC clocking, and wireless transceivers. Key specifications include low additive jitter (225 fs rms), sub‑10 ps channel‑to‑channel skew, and operation over –40 °C to +85 °C.
| VCO Frequency Range | 2.30 GHz – 2.65 GHz |
|---|---|
| Operating Temperature Range | −40 °C to +85 °C |
| Maximum LVPECL Output Frequency | 2.95 GHz |
| Output Differential Voltage (typical) | 550 mV |
The on‑chip VCO tunes from 2.30 GHz to 2.65 GHz.
The device provides six LVPECL outputs arranged in three pairs.
It is specified for operation from –40 °C up to +85 °C.