74HC/HCT138 is a high-speed Si-gate CMOS device with 3-to-8 line decoder/demultiplexer function, which can be used for memory chip selection decoding.
The 74HC/HCT138 provides three binary‑weighted address inputs and eight mutually exclusive active‑LOW outputs, making it suitable for memory chip‑select decoding and expansion to larger decoders. It features two active‑LOW enable inputs (E1, E2) and one active‑HIGH enable input (E3), allowing flexible parallel expansion.
Typical specifications include a propagation delay of about 6 ns, standard output capability, and a supply voltage of 5 V. The device is pin‑compatible with low‑power Schottky TTL and complies with JEDEC standard 7A. Detailed pin descriptions, functional tables, and electrical characteristics are provided in the datasheet.
| Supply voltage (VCC) | 5 V |
|---|
It is a 3‑to‑8 line decoder/demultiplexer with inverting (active‑LOW) outputs.
The device accepts three binary‑weighted address inputs (A0, A1, A2).