This document is a technical specification of K4S640832K Synchronous DRAM Rev. 1.1 February 2006, which contains various parameters information of the product.
The K4S640832K is a 64 Mb synchronous DRAM organized as 2 M × 8 bits with four banks. It supports JEDEC‑standard 3.3 V operation, LVTTL‑compatible address multiplexing, and features such as auto‑refresh, burst lengths of 1‑8, and selectable CAS latencies of 2 or 3.
The document lists detailed ordering information, package dimensions (54‑pin TSOP‑II), absolute maximum ratings, recommended DC operating conditions, capacitance values, and timing characteristics. Pin‑out tables, functional block diagrams, and a simplified truth table are also included for design reference.
| Capacity | 64 Mb |
|---|---|
| Supply Voltage | 3.3 V (JEDEC standard) |
| Maximum Frequency | 133 MHz (CL=3) |
| Package Type | 54‑pin TSOP(II) |
| Refresh Period | 64 ms (4K cycle) |
| Storage Temperature Range | -55 °C to +150 °C |
| Input Logic High Voltage (VIH) | 2.0 V – 3.0 V (Vpp+0.3) |
| Input Logic Low Voltage (VIL) | -0.3 V – 0 V |
The recommended supply voltage is 3.0 V to 3.6 V with a typical value of 3.3 V.
The part can operate up to 133 MHz (CL = 3) in the 8‑bit package.
It is supplied in a 54‑pin TSOP(II) package.
The device uses a 64 ms refresh period (4K cycle).