This document describes the specifications of Samsung Electronics' SDRAM 64Mb H-die, including different models with various interfaces and packages, as well as its high-performance CMOS technology and synchronous design features.
The document provides a detailed description of Samsung's 64Mb H‑die CMOS SDRAM, available in x4, x8, and x16 data widths. It lists the device organization, package type (54‑pin TSOP‑II, RoHS‑compliant), and key features such as JEDEC‑standard 3.3 V operation, four‑bank architecture, and programmable burst length and latency.
Electrical characteristics, absolute maximum ratings, and timing parameters are given for typical operating conditions (0 °C to 70 °C). The datasheet also includes pin‑function tables, truth tables for command decoding, and AC test conditions for high‑speed operation up to 133 MHz.
| Package type | 54‑pin TSOP‑II (400 mil × 875 mil, 0.8 mm pitch) |
|---|---|
| Supply voltage (VDD, VDDQ) | 3.0 V – 3.6 V (typical 3.3 V) |
| Operating temperature range | -55 °C to +150 °C |
| CAS latency | 2 or 3 clock cycles |
| Burst length options | 1, 2, 4, 8, Full page |
The recommended supply voltage is 3.3 V, with a minimum of 3.0 V and a maximum of 3.6 V.
It uses a 54‑pin TSOP‑II package measuring 400 mil × 875 mil with a 0.8 mm pin pitch.