TMS320C5x, TMS320LC5x digital signal processors feature a powerful 16-bit TMS320C5x CPU, single-cycle 16×16-bit multiply/add, 224K×16-bit maximum addressable external memory space, multiple packaging options, low power dissipation, and power-down modes.
The TMS320C5x and TMS320LC5x families are 16‑bit digital signal processors featuring a Harvard architecture, on‑chip peripherals, and a high‑performance instruction set. They can execute up to 50 MIPS and include features such as single‑cycle multiply/add, multiple PLL clocking options, and JTAG boundary‑scan.
The datasheet lists memory capacities (up to 224 K × 16‑bit external memory, various on‑chip ROM and RAM sizes), detailed pin‑out tables for PQ and PBK packages, power‑dissipation figures, and the five available package styles. It also contains regulatory and warranty notices for TI products.
| CPU architecture | 16‑bit TMS320C5x CPU |
|---|---|
| Single‑cycle instruction time (5 V) | 20‑50 ns |
| Maximum external memory | 224 K × 16‑bit (64 K program, 64 K data, 64 K I/O, 32 K global) |
| On‑chip program ROM | 2 K to 32 K × 16‑bit single‑access |
| On‑chip RAM (SARAM) | 1 K to 9 K × 16‑bit single‑access |
| Single‑cycle multiply/add | 16 × 16‑bit |
| Power consumption (5 V, 40 MHz, average) | 47 mA (2.35 mA/MIP) |
Up to 224 K × 16‑bit, comprising 64 K program, 64 K data, 64 K I/O, and 32 K global memory.
The device provides a single‑cycle 16 × 16‑bit multiply/add operation.
Approximately 47 mA average (2.35 mA/MIP).