TMS320C203, TMS320C209, TMS320LC203 are digital signal processors designed by Texas Instruments based on the T320C2xLP Core CPU. The architecture has six internal buses for increased parallelism and performance. Features of the series include a 32-bit ALU/Accumulator, a 16 x 16-bit single-cycle multiplier with a 32-bit product, block moves for data, program, and I/O space, and a hardware repeat instruction.
The TMS320C2xx family of 16‑bit fixed‑point digital signal processors combines a six‑bus Harvard architecture core with low‑power CMOS technology. The devices offer up to 40 MIPS performance (C203) and include on‑chip RAM, optional ROM, and a range of clocking options.
Key peripherals include a 20‑bit timer, UART (C203 only), a synchronous serial port, general‑purpose I/O, and multiple external interrupt lines. The datasheet also lists package options (100‑pin and 80‑pin TQFP) and detailed pin‑level descriptions for data, address, and control signals.
| Instruction cycle time (C203) | 50 ns @5 V |
|---|---|
| Instruction cycle time (C209) | 35 ns @5 V |
| Power dissipation (3.3 V) | 1.1 mA/MIPS |
| On‑chip dual‑access data RAM | 544 × 16‑bit words |
| On‑chip program RAM (C209 only) | 4 K × 16‑bit words |
| On‑chip program ROM (C209 only) | 4 K × 16‑bit words |
| External addressable memory space | 224 K × 16‑bit words |
| Package (C203) | 100‑pin TQFP |
| Package (C209) | 80‑pin TQFP |
| Number of external interrupts | Four |
The TMS320C203 has an instruction cycle time of 50 ns when powered at 5 V.
It provides 544 × 16‑bit words of dual‑access data RAM on‑chip.
The TMS320C209 is offered in an 80‑pin thin‑quad flat package (TQFP).
At 3.3 V the device dissipates 1.1 mA per MIPS of performance.