TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS
The TMS320C5x generation of Texas Instruments digital signal processors offers a 16‑bit CPU with single‑cycle instruction execution, up to 50 MIPS performance, and a flexible Harvard architecture. On‑chip memory includes configurable ROM and RAM sizes, while external memory can address up to 224 K × 16‑bit locations.
The document provides complete pin‑out tables for the PQ and PBK packages, describes serial, TDM, and host‑port interfaces, and lists power‑supply pins and JTAG boundary‑scan support. Package options range from 100‑pin QFP to 144‑pin thin QFP, and power‑down modes reduce consumption to a few microamps.
| CPU architecture | 16‑bit TMS320C5x CPU |
|---|---|
| Single‑cycle instruction time (5 V) | 20‑50 ns |
| Maximum external memory | 224 K × 16‑bit (64 K program, 64 K data, 64 K I/O, 32 K global) |
| On‑chip ROM size options | 2 K, 4 K, 8 K, 16 K, 32 K × 16‑bit |
| On‑chip SARAM size options | 1 K, 3 K, 6 K, 9 K × 16‑bit |
| Dual‑access RAM (DARAM) | 1 K × 16‑bit |
| Typical power consumption (5 V, 40 MHz) | 47 mA average (2.35 mA/MIP) |
| JTAG / Boundary‑scan support | IEEE Standard 1149.1T Test‑Access Port |
It can address up to 224 K × 16‑bit, comprising 64 K program, 64 K data, 64 K I/O, and 32 K global memory.
The average current draw is 47 mA (2.35 mA per MIP) under those conditions.
Yes, it includes an IEEE Standard 1149.1T Test‑Access Port for JTAG boundary‑scan.