This document is an application note for ATV2500, which introduces how ATV2500 is used to incorporate multiple control or logic functions into a single programmable logic device
The document introduces the ATV2500 programmable logic device and shows how it can generate all control and addressing functions for a simple NTSC video frame grabber. It describes the video basics, timing requirements, and the overall architecture that includes A/D and D/A conversion, RAM buffering, and a vertical sync detector.
Implementation details cover the schematic, the use of a 256 K × 8 static RAM as a frame buffer, and the ABEL source code that defines the control state machine, address counter, and sync detection logic. The note also provides resource allocation tables and test‑vector strategies for verifying the design.
| Macrocell composition | 2 flip‑flops, 12 product terms (split into 3 sum terms), and an output enable per macrocell |
|---|---|
| Flip‑flop features | Clock term and asynchronous reset term per flip‑flop |
| Preset capability | Groups of four or eight flip‑flops share a synchronous preset product term |
A sample frequency of 7.5 MHz was chosen, which is a little more than twice the NTSC color‑burst frequency.
The total number of samples required for each frame is 253,245 (7.5 MHz × 16.683 ms × 2).
A 256 K × 8 static RAM module is used as the frame buffer memory.