Atmel ATV750 Application Note: Using a PLD as a System Controller in an I/O Bus Based System

About this manual

The note describes the evolution of programmable logic devices (PLDs) and highlights the features of third‑generation devices such as the Atmel ATV750. It explains how the ATV750’s extra registers, independent feedback paths, and asynchronous clocks enable the implementation of a peripheral controller/bus interface for an 80186‑based system.

A detailed example shows the ATV750 controlling a custom encryption chip, handling address decoding, data transfer, and status signaling. The document includes logic equations, timing details (8 MHz system clock), and a state‑machine diagram, illustrating how the design fits into a single ATV750 with about 80 % gate utilization.

What's inside

• Summary
• PLD Evolution
• Feature Evolution
• System Application
• The System
• The Microprocessor Bus
• Tackling the I/O Bus
• The Chip Interface
• Starting the Peripheral Chip
• Multiplexing Flip‑flop Inputs and /O Pins

Specifications

Frequently asked questions

How many flip‑flops does the Atmel ATV750 provide?

The ATV750 provides 20 flip‑flops.

What clock speed is used for the example system?

The example system uses an 8 MHz clock.

How many output pins are available on the ATV750?

The ATV750 has ten output pins.

What utilization percentage does the design achieve in the ATV750?

The design uses about 80 % of the ATV750’s gate capacity.