This product is a high-density, high-performance, electrically erasable complex programmable logic device, with features of 64 macrocells, 5 product terms per macrocell, expandable to 40 per macrocell, 44, 68, 84, 100 pins, maximum pin-to-pin delay of 7.5 ns, registered operation speed up to 125 MHz, and enhanced routing resources
The ATF1504AS is a high‑performance, high‑density complex programmable logic device (CPLD) from Atmel. It offers 64 macrocells, up to 68 bi‑directional I/O pins, and flexible macrocell resources such as product terms, flip‑flops, and programmable output options. The device supports in‑system programming via a standard 4‑pin JTAG interface and includes security features like a programmable fuse and user signature.
Power‑management features include automatic standby, programmable pin‑keeper circuits, reduced‑power bits per macrocell, and an optional power‑down mode that can lower current consumption below 10 mA. Mechanical details such as package dimensions for PLCC, TQFP, and PQFP options are also provided.
| Number of macrocells | 64 |
|---|---|
| Maximum pin‑to‑pin delay | 7.5 ns |
| Registered operation speed | 125 MHz |
| I/O pins | up to 68 bi‑directional I/O pins |
| Program/erase cycles | 10,000 |
| Data retention | 20 years |
| ESD protection | 2000 V |
| Latch‑up immunity | 200 mA |
The ATF1504AS contains 64 macrocells.
The maximum pin‑to‑pin delay is 7.5 ns.
It uses the industry‑standard 4‑pin JTAG interface (IEEE Std. 1149.1).