This white paper introduces a method for improving the I/O connectivity and logic reusability of Complex Programmable Logic Devices (CPLDs). This method, called Logic Doubling, works by splitting the logic circuit into two logic blocks and using different logic circuits in each logic block. This allows CPLDs to support more I/O ports and improve the reusability of logic circuits.
The paper describes the limitations of earlier CPLDs and introduces Atmel's Logic Doubling approach, which provides 100 % I/O connectivity, wider fan‑in, and independent macrocell output‑enable. It details the architectural enhancements in the ATF15xx family (ATF1500, ATF1502, ATF1504, ATF1508) and how they improve logic utilization.
Reference designs such as a parallel I/O expander, keypad scanner, and fast parallel memory interface illustrate practical use of the architecture. The document also covers fitter and verification capabilities, including global clocks, fuse counts, and macrocell routing resources.
| Macrocell count – ATF1502 | 32 |
|---|---|
| Macrocell count – ATF1504 | 64 |
| Macrocell count – ATF1508 | 128 |
| Fan‑in (ATF1500) | 68 |
| Global clocks | 3 (selectable polarity) |
| Fuse count – ATF1502 | 25 000 |
Logic Doubling is Atmel's CPLD architecture that provides 100 % connectivity, wider fan‑in, independent macrocell output‑enable, and dual feedback paths to increase usable logic resources.
The ATF15xx family provides three global clocks, each selectable for rising or falling edge polarity.
The ATF1500 offers a fan‑in of 68, the highest among the ATF15xx devices.