The AD6652 is a 12-bit, 65 MSPS IF to baseband diversity receiver featuring integrated dual-channel ADC, sample rates up to 65 MSPS, IF sampling frequencies up to 200 MHz.
The AD6652 is a mixed‑signal IF‑to‑baseband receiver that integrates dual 12‑bit, 65 MSPS ADCs and a wideband digital downconverter (DDC). It targets communications, imaging, medical ultrasound, instrumentation and test equipment, offering low cost, small size and flexible analog input ranges.
Key features include a duty‑cycle stabilizer, dual 16‑bit parallel and 8‑bit link output ports, programmable FIR filters, and built‑in self‑test. The device operates from 3.0 V AVDD, 2.5 V VDD and 3.3 V VDDIO, and provides extensive timing and electrical specifications for system integration.
| AVDD Supply Voltage | 3.0 V |
|---|---|
| VDD Supply Voltage | 2.5 V |
| VDDIO Supply Voltage | 3.3 V |
It requires AVDD = 3.0 V, VDD = 2.5 V, and VDDIO = 3.3 V.
Yes, the device includes a duty‑cycle stabilizer to compensate clock variations.