The DS26401 is an octal, software-selectable T1, E1 or J1 framer. It is composed of eight framer/formatters and a system (backplane) interface. Each framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26401 also includes a full-feature BERT device, which can be used with any of the eight T1/E1 ports, and an internal clock adapter useful for creating synchronous, high frequency backplane timing. The DS26401 is controlled through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola operation.
The DS26401 is an octal, software‑selectable T1, E1 or J1 framer composed of eight independent framer/formatters and a system backplane interface. Each framer includes an HDLC controller that can be mapped to any DS0, FDL (T1) or Sa (E1) bit, and the device is controlled via an 8‑bit parallel port configurable for Intel or Motorola non‑multiplexed operation.
Key features include a full‑feature BERT that can be assigned to any port, an internal clock generator offering 16.384 MHz, 8.192 MHz, 4.096 MHz or 2.048 MHz outputs, a maximum backplane rate of 16.384 MHz, and support for a wide range of telecom standards (ANSI T1.102, ITU‑G.704, G.706, etc.). The device operates from a single 3.3 V supply with 5 V‑tolerant inputs and is available in a 17 mm × 17 mm, 256‑pin BGA package.
| Package | 17mm x 17mm, 256‑Pin BGA (1.00mm Pitch) |
|---|---|
| Supply Voltage | Single 3.3 V Supply with 5 V Tolerant Inputs |
| Maximum Backplane Rate | 16.384 MHz |
| Internal Clock Generator Frequencies | 16.384 MHz, 8.192 MHz, 4.096 MHz, 2.048 MHz |
| Operating Temperature (DS26401N) | -40 °C to +85 °C |
It is controlled through an 8‑bit parallel port that can be configured for non‑multiplexed Intel or Motorola operation.
Yes, the device includes a full‑feature BERT that can be mapped to any of the eight ports.