This page provides manuals, user guides, handbooks, specifications, and maintenance instructions for Industrial. View online or download for free. Showing page 3493.
This document is a HONGFA RELAY General Purpose Power Relays product manual, which introduces the product's features and characteristics, including product type, model, working voltage, current, contact capacity, ambient temperature, and service life.
The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high-speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2.
The SY10/100EL15 is a low skew 1:4 clock distribution chip designed specifically for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to VCC via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single- ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.
The document is copyrighted by ICminer.com Electronic-Library Service. It describes the features and characteristics of the ICminer.com Electronic-Library Service.
GT5 Series is a connector for coaxial cables, which has various types and configurations: in-line, board mounted, combinations of coaxial cable with signal/power, Multi-position and color/keying variations.
This document describes the features and characteristics of the SY10/100E167 product, including minimum operating frequency, extended VEE range, maximum clock to output delay, etc.
The SY10/100E158 is a 5-bit 2:1 multiplexer with differential outputs, designed for use in new, high-performance ECL systems. The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed through.
The SY10E157 is a quad 2:1 multiplexer with differential outputs manufactured by Micrel. It features individual select controls and is suitable for random logic designs.
The SY10/100E156 is a 3-bit 4:1 MUX-Latch designed for use in new, high-performance ECL systems. It features differential outputs, asynchronous Master Reset, dual latch enables, fully compatible with industry standard 10KH, 100K ECL levels, internal 75KΩ input pulldown resistors, and is available in a 28-pin PLCC package.
This document describes the features and characteristics of GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D) 9Mb Pipelined and Flow Through Synchronous NBT SRAM, including user-configurable Pipeline and Flow Through mode, NBT functionality, compatibility with other SRAMs, JTAG compatibility, on-chip write parity checking, power supply and interface options, etc.
The SY10/100E154 is a 5-bit 2:1 multiplexer followed by latches with differential outputs, designed for use in new, high-performance ECL systems. It features asynchronous master reset, dual latch-enables, and is fully compatible with industry standard 10KH, 100K ECL levels. The product is available in a 28-pin PLCC package.
