This document describes the features and characteristics of the SY10/100E167 product, including minimum operating frequency, extended VEE range, maximum clock to output delay, etc.
The SY10E167 and SY100E167 are 6‑bit 2:1 multiplexers with integrated D‑flip‑flops, designed for high‑performance ECL systems. They feature dual external clock inputs (CLK1, CLK2) that are OR‑gated, a select input to choose data lines, and single‑ended outputs. The devices operate asynchronously and are fully compatible with standard 10 kH and 100 kH ECL levels.
Key specifications include a minimum operating frequency of 1 GHz, a VEE range of –4.2 V to –5.5 V, propagation delays of 450‑800 ps, and a 28‑pin PLCC package. Ordering codes are SY10E167JC, SY10E167JCTR, SY100E167JC, and SY100E167JCTR, all commercial grade.
| Minimum operating frequency | 1000 MHz |
|---|---|
| VEE voltage range | -4.2 V to -5.5 V |
| Maximum toggle frequency (fMAX) | 1000‑1400 MHz |
| Propagation delay (tPLH) | 450‑800 ps |
| Setup time (SEL) | 125 ps typ |
| Reset recovery time (tRR) | 750‑550 ps |
| Minimum pulse width (tPw) | 400 ps |
| Input HIGH current (MH) | 150 µA |
| Package type | 28‑pin PLCC |
The devices operate at a minimum frequency of 1000 MHz.
The VEE pin can handle voltages from –4.2 V to –5.5 V.
Both ICs are supplied in a 28‑pin PLCC package.
The SY10E167 is available under the ordering codes SY10E167JC and SY10E167JCTR, both 28‑pin PLCC commercial parts.