Industrial

The ISL8308XE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output and receiver input is protected against ±15kV ESD strikes without latch-up. Unlike competitive products, this Intersil family is specified for 10% tolerance supplies (4.5V to 5.5V). These devices have very low bus currents (+125µA/-75µA), so they present a true “1/8 unit load” to the RS-485 bus. This allows up to 256 transceivers on the network without violating the RS-485 specification’s 32 unit load maximum, and without using repeaters. For example, in a remote utility meter reading system, individual meter readings are routed to a concentrator via an RS-485 network, so the high allowed node count minimizes the number of repeaters required. Data for all meters is then read out from the concentrator via a single access port, or a wireless link. Receiver (Rx) inputs feature a “Full Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, shorted, or terminated but undriven. The ISL83080E, ISL83082E, ISL83083E and ISL83085E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Slew rate limited drivers also prevent overshoot on the RS-485 line when the transmitter is disabled.

ISL6523A is a power control chip produced by ISL company. It integrates two PWM controllers, two linear controllers, as well as monitoring and protection functions into a 28-pin SOIC package. One PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. The second PWM controller supplies the computer system’s AGTL+ 1.2V bus power with a standard buck converter. The linear controllers regulate power for the 1.5V AGP bus and the 1.8V power for the chipset core voltage and/or cache memory circuits. The ISL6523A includes an Intel VRM8.5 compatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the microprocessor core-targeted PWM output voltage from 1.050V to 1.825V in 25mV steps. The precision reference and voltage-mode control provide ±1% static regulation. The second PWM controller’s output provides a voltage level of 1.2V with ±3% accuracy. The linear regulators use external N-channel MOSFETs or bipolar NPN pass transistors to provide fixed output voltages of 1.5V ±3% (VOUT3) and 1.8V ±3% (VOUT4). The ISL6523A monitors all the output voltages. A delayed-rising VTT (standard buck output) Power Good signal is issued before the core PWM starts to ramp up. Another system Power Good signal is issued when the core is within ±10% of the DAC setting and all output voltages are normal.

This PDF document introduces the information of Murata's IRA series pyroelectric infrared sensors, including models, dimensions, working temperature range, applications, etc.

IPB06N03LA IPI06N03LA, IPP06N03LA OptiMOS®2 Power-Transistor is a product of Texas Instruments. It has very low on-resistance, excellent thermal resistance, etc.

This document describes the features and characteristics of Semelab's IP1R17A and IP3R17A fixed negative voltage regulators, including line regulation, load regulation, output accuracy, etc.

This document describes the features and characteristics of IDT's products, including high-performance 64-bit microprocessor, single/double precision floating-point unit, high-speed caches, and flexible bus interface.

This document describes the features and characteristics of the FIFO dual-port memory from Integrated Device Technology, Inc., including the 64 x 4 or 64 x 5 organization, low power consumption, high-speed data communications applications, etc.

This document describes the features and characteristics of IDT72261LA and IDT72271LA CMOS SuperSync FIFOs, including memory organizations, read/write cycle time, data latency time, low power mode, reset functions, data status flags, etc.

The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V3577/79 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter tracks the address during burst mode to ensure that data is provided to the system during the burst.

IDT70V27S/L is a dual-port memory produced by IDT company. It has high-speed access, low power consumption, separate upper and lower byte control, dual chip enables, bus width expansion, busy flag and interrupt flag, port arbitration logic, semaphore logic, fully asynchronous operation and other features.

This document is a functional block diagram of DSC-5632/3 published by Integrated Device Technology, Inc. in November 2003. It includes features such as busy and interrupt flags, on-chip port arbitration logic, full on-chip hardware support of semaphore signaling between ports, fully asynchronous operation from either port, separate byte controls, dual-port memory cells, high performance and high reliability.

IDT6116SA/LA is a high-performance static RAM manufactured by IDT company using CMOS technology. It has fast access and low power consumption. The product has military and commercial temperature ranges and meets the MIL-STD-833, Class B standard.