Industrial Manuals

The AD9520-0 is a low phase noise phase-locked loop (PLL) clock generator with integrated 2.8 GHz VCO, featuring 12 LVPECL outputs and 24 CMOS outputs.

The AD9520-2 is a 12 LVPECL/24 CMOS output clock generator with integrated 2.2 GHz VCO. It features low phase noise and phase-locked loop (PLL).

AD9520-3 is a 12 LVPECL/24 CMOS output clock generator with integrated 2GHz VCO.

The AD9520-5 is a low phase noise, phase-locked loop (PLL) that supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz, 1 differential or 2 single-ended reference inputs, accepts CMOS, LVDS or LVPECL references to 250 MHz, accepts 16.67 MHz to 33.3 MHz crystal for reference input, optional reference clock doubler, reference monitoring capability, automatic and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching, glitch-free switchover between references, automatic recovery from holdover, digital or analog lock detect, selectable zero delay operation, 12 1.6 GHz LVPECL outputs divided into 4 groups, each group of 3 has a 1 to 32 divider with phase delay, additive output jitter as low as 225 fs rms, channel-to-channel skew grouped outputs <16 ps, each LVPECL output can be configured as differential or single-ended, and the output frequency and phase offset can be selected.

This document describes a 12 LVDS/24 CMOS output clock generator with an integrated 2.8 GHz VCO. It features low phase noise, phase-locked loop (PLL), support for external 3.3 V/5 V VCO/VCXO, and various reference inputs.

The product is a 12-channel LVDS/24-channel CMOS output clock generator with an integrated 2.4 GHz VCO, low phase noise, phase-locked loop (PLL).

The AD9522-2 is a clock generator from Analog Devices that provides 12 LVDS and 24 CMOS outputs. It has low phase noise, frequency synthesis, and more.

AD9522-3 is a 12 LVDS/24 CMOS output clock generator with integrated 2 GHz VCO.

AD9522-4 is a 12 LVDS/24 CMOS output clock generator with integrated 1.6 GHz VCO.

AD9522-5 is a low phase noise, phase-locked loop (PLL) from Analog Devices. This chip supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz, supports 1 differential or 2 single-ended reference inputs, accepts CMOS, LVPECL or LVDS references to 250 MHz, accepts 16.62 MHz to 33.33 MHz crystal as reference input, has an optional reference clock doubler, supports reference monitoring capability, has auto and manual reference switchover/holdover modes with selectable revertive/nonrevertive switching, glitch-free switchover between references, automatic recovery from holdover, supports digital or analog lock detect, optional zero delay operation. This chip has 12 800 MHz LVDS outputs, divided into 4 groups, each group of 3 has a 1-to-32 divider with phase delay. The additive broadband jitter is as low as 242 fs rms, grouped outputs channel-to-channel skew < 60 ps, each LVDS output can be configured as an independent output or connected to the PLL's internal 1-to-32 divider.

The document provides information about the features and characteristics of the AD9540 Rev. A low jitter clock generator, including excellent intrinsic jitter performance, programmable parameters and profiles, supported input and output frequencies, etc.

AD9549 Rev. 0 is a dual input network clock generator/synchronizer with flexible reference inputs, auto/manual holdover modes, and switchover modes. It also features excellent stability in holdover mode and a high-speed digitally controlled oscillator (DCO) core DDS.

The AD9551 is a multiservice clock generator that can perform translation between any two standard network rates. It has dual reference inputs and dual clock outputs, supports standard forward error correction (FEC) rates, and features holdover operation and hitless switchover capabilities.