The AD9520-0 is a low phase noise phase-locked loop (PLL) clock generator with integrated 2.8 GHz VCO, featuring 12 LVPECL outputs and 24 CMOS outputs.
The AD9520-0 provides a multi‑output clock distribution solution with sub‑picosecond jitter, an on‑chip PLL, and a VCO that tunes from 2.53 GHz to 2.95 GHz. It supports both LVPECL and CMOS outputs, optional reference clock doubling, zero‑delay operation, and serial control via SPI or I²C.
The device is supplied in a 64‑lead LFCSP package, operates from a single 3.3 V supply, and includes an EEPROM for non‑volatile configuration. It is intended for low‑jitter clock distribution in high‑speed data‑converter, communication, and instrumentation applications.
| VCO Frequency Range | 2.53 GHz – 2.95 GHz |
|---|---|
| Power Supply VS | 3.135 V min – 3.3 V typ – 3.465 V max |
| LVPECL Output Rise Time | 130 ps min – 170 ps max |
| Number of LVPECL Outputs | 12 |
| Reference Input Frequency Range | 0 Hz – 250 MHz |
The on‑chip VCO tunes from 2.53 GHz to 2.95 GHz.
VS must be between 3.135 V and 3.465 V (typical 3.3 V), VS_DRV between 2.375 V and 3.465 V, and VCP up to 5.25 V.
The AD9520‑0 provides twelve LVPECL outputs.
Both rise and fall times are specified as 130 ps to 170 ps.