Altera manuals, page 8
ALTERA Nios II Custom Instruction user manual
The Nios II Custom Instruction User Guide describes how to use custom instructions on a Nios II processor and provides detailed information on writing, assembling, linking, and downloading custom instructions.
ALTERA MAX 9000 handbook(2)
ALTERA MAX 9000 handbook(1)
ALTERA MAX 9000 handbook
MAX 9000 Programmable Logic Device Family is a high-performance CMOS EEPROM-based programmable logic device (PLD) built on third-generation Multiple Array MatriX (MAX®) architecture.
ALTERA MAX 7000B handbook
ALTERA MAX 7000 handbook(2)
The MAX 7000 is a high-performance EEPROM programmable logic device (PLD) produced by Altera Corporation. It is based on the second-generation MAX architecture. The MAX 7000 series devices have 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, and the ISP circuitry meets the IEEE Std. 1532 standard. The MAX 7000 series includes 5.0 V MAX 7000 devices and 5.0 V ISP based MAX 7000S devices. When the MAX 7000S device has 128 or more macrocells, it has an internal JTAG boundary scan test (BST) circuit. The MAX 7000 series devices have logic densities ranging from 600 to 5,000 usable gates, and have 5 ns pin-to-pin logic delays, which can achieve up to 175.4 MHz counter frequencies (including interconnect). PCI-compatible devices are available.
ALTERA MAX 7000 handbook(1)
The MAX 7000 is a high-performance, EEPROM-based PLD from Altera Corporation. It is based on the second-generation MAX architecture and includes both 5.0V MAX 7000 and 5.0V ISP-based MAX 7000S devices. The MAX 7000 family has a logic density range of 600 to 5,000 usable gates and a 5ns pin-to-pin logic delay.
ALTERA MAX 7000A handbook(3)
MAX 7000A is a high-performance 3.3V EEPROM-based programmable logic device (PLD) produced by Altera Corporation. Its architecture is the second-generation Multiple Array MatriX (MAX). It supports 3.3V in-system programmability (ISP) and IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability. Moreover, MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532, while EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532. MAX 7000A also supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71.
Altera Corporation EPM7064 EPM7064S Dedicated Pin-Outs ver. 1.0 technology data
This document provides detailed information about the pin-outs and input/output pins of Altera Corporation's EPM7064 and EPM7064S products.
ALTERA MAX 7000A handbook(2)
MAX 7000A is a high-performance 3.3-V EEPROM-based programmable logic devices (PLDs) from Altera Corporation, built on second-generation Multiple Array MatriX (MAX®) architecture, with 3.3-V in-system programmability (ISP) and advanced pin-locking capability through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, and it also supports IEEE Std. 1149.1 compliant built-in boundary-scan test (BST) circuitry and JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
ALTERA MAX 7000A handbook(1)
MAX 7000AE is a high-performance 3.3V EEPROM-based programmable logic device (PLD) built on second-generation Multiple Array MatriX (MAX) architecture. It supports 3.3V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability. The device also features built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 and supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71. It is pin-compatible with the popular 5.0V MAX 7000S devices and offers high-density PLDs ranging from 600 to 10,000 usable gates.
ALTERA MAX 7000 handbook
ALTERA MAX 7000A handbook
This data sheet provides detailed information about the Altera MAX 7000A series of programmable logic devices, including models, pins, functions, and packages.
ALTERA EPM5016 to EPM5192 EPLDS handbook
Altera Corporation EPM3512A Dedicated Pin-Outs ver. 1.0 technology data
This document describes the pin-out of the EPM3512A chip. The EPM3512A is a chip with 208-pin PQFP package and 256-pin FineLine BGA package. The document provides information about the functions and connections of different pins.