Altera Manuals

Altera Corporation has released preliminary release notes for the SerialLite II MegaCore function. This function contains the following information: system requirements, new features and enhancements, Adobe Reader version 5.0 or higher for viewing PDF documentation, obtaining and installing the SerialLite II MegaCore function, contacting Altera, and revision history.

This document is a preliminary release notes for the HyperTansport MegaCore function version 1.4.0 released by Altera company. It contains the system requirements, new features, enhancements, fixes, and how to obtain and install the function.

This chapter describes the hardware features that support high-speed memory interfacing for each double data rate (DDR) memory standard in HardCopy® III devices. HardCopy III devices feature delay-locked loops (DLLs), phase-locked loops (PLLs), dynamic on-chip termination (OCT), read-and-write leveling, and deskew circuitry. This chapter contains the following sections:...

This document describes the I/O features of Altera's Cyclone V devices, including support for different types of I/O standards and requirements.

This document introduces how to use Altera's Stratix II GX FPGA for thermal design

This document is about the pin information of EPM240 device, including IO/GCLK0, IO/GCLK1, IO/GCLK2, IO/GCLK3, IO/DEV_OE, IO/DEV_CLRn, TDI, TMS, TCK, TDO, GNDINT, GNDIO, VCCINT, VCCIO1, VCCIO2

This is a document about Altera Cyclone III device family pin connection guidelines

This document is an introduction to PLL design and usage in Altera Cyclone FPGAs

Describes the I/O standards supported by the Altera Stratix and Stratix GX devices

This document describes a product called Bank Number VREF Bank Pin. The product has multiple pins for different functions, including configuration and optional functions.

This is a PDF file that mainly introduces the pin functions, configuration functions, dedicated Tx/Rx channels, and analog LVDS output channels of the H1517 device.

This document describes the bank number VREF pin names and functions for different models, as well as configuration functions and channel information.

This document describes the DQ groups in different modes, including x8/x9 mode, x16/x18 mode, and x32/x36 mode. It also introduces the DQ groups for DQS mode and non-DQS mode, and provides some specific DQ group configurations.