Altera Manuals - Page 12

Altera manuals, page 12

• Altera Corporation EP1K10 Device Pin-Outs Manual

  EP1K10 device pin-out

• Altera Corporation SerialLite II MegaCore Function v1.0.1 Release Notes Manual

  Altera Corporation has released preliminary release notes for the SerialLite II MegaCore function. This function contains the following information: system requirements, new features and enhancements, Adobe Reader version 5.0 or higher for viewing PDF documentation, obtaining and installing the SerialLite II MegaCore function, contacting Altera, and revision history.

• Altera Corporation HyperTransport MegaCore Function v1.4.0 Release Notes Manual

  This document is a preliminary release notes for the HyperTansport MegaCore function version 1.4.0 released by Altera company. It contains the system requirements, new features, enhancements, fixes, and how to obtain and install the function.

• Altera Corporation External Memory Interfaces in HardCopy III Devices Manual

  This chapter describes the hardware features that support high-speed memory interfacing for each double data rate (DDR) memory standard in HardCopy® III devices. HardCopy III devices feature delay-locked loops (DLLs), phase-locked loops (PLLs), dynamic on-chip termination (OCT), read-and-write leveling, and deskew circuitry. This chapter contains the following sections:...

• Altera Cyclone V Device Handbook I/O Features Manual

  User Manual 60 pages · 1.7 MB · EN

  This Altera Cyclone V device handbook chapter describes I/O features, supported standards, banks, and design considerations.

• Altera Corporation High-Speed Board Design Advisor: Thermal Management Manual

  This document introduces how to use Altera's Stratix II GX FPGA for thermal design

• Altera Corporation Dedicated Pin Information for the MAX II EPM2210 EPM2210G Manual

• Altera Corporation Pin Information for the MAX II EPM240 EPM240G Devices Manual

  This document is about the pin information of EPM240 device, including IO/GCLK0, IO/GCLK1, IO/GCLK2, IO/GCLK3, IO/DEV_OE, IO/DEV_CLRn, TDI, TMS, TCK, TDO, GNDINT, GNDIO, VCCINT, VCCIO1, VCCIO2

• Altera Corporation Cyclone III Pin Connection Guidelines Manual

  This is a document about Altera Cyclone III device family pin connection guidelines

• Altera Corporation Cyclone Handbook Volume 1 Chapter 6. Using PLLs in Cyclone Manual

  This document is an introduction to PLL design and usage in Altera Cyclone FPGAs

• Altera Corporation Stratix Device Handbook Volume 2 Section 3 Chapter 4 Manual

  Describes the I/O standards supported by the Altera Stratix and Stratix GX devices

• Altera Corporation Pin Information for the Stratix EP1S25 Device Manual

  This document describes a product called Bank Number VREF Bank Pin. The product has multiple pins for different functions, including configuration and optional functions.

• Altera Corporation Pin Information for the Stratix IV GT EP4S40G5 Device Manual

  This is a PDF file that mainly introduces the pin functions, configuration functions, dedicated Tx/Rx channels, and analog LVDS output channels of the H1517 device.

• Altera Corporation Pin Information for the Stratix IV GX EP4SGX180 Device Manual

  This document describes the bank number VREF pin names and functions for different models, as well as configuration functions and channel information.

• Altera Corporation Pin Information for the Stratix II GX EP2SGX90 Device Manual

  This document describes the DQ groups in different modes, including x8/x9 mode, x16/x18 mode, and x32/x36 mode. It also introduces the DQ groups for DQS mode and non-DQS mode, and provides some specific DQ group configurations.

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