ANALOG Manuals

The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 2 inputs/12 LVDS outputs to 2 inputs/24 CMOS outputs.

ADCLK846 is a low power clock fanout buffer with selectable LVDS/CMOS outputs. It can provide up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs. Each channel consumes less than 16 mW power and has an integrated jitter of 54 fs (12 kHz to 20 MHz) and additive broadband jitter of 100 fs. It has a propagation delay of 2.0 ns (LVDS), output rise/fall time of 135 ps (LVDS), and output-to-output skew of 65 ps (LVDS). This product is suitable for applications such as low jitter clock distribution, clock and data signal restoration, level translation, wireless communications, wired communications, medical and industrial imaging, ATE, and high performance instrumentation.

The AD9573 is a PCI-Express clock generator IC with a fully integrated VCO/PLL core, low jitter, and low phase noise. It is suitable for line cards, switches, routers, CPU/PCIe applications, and other applications with demanding phase noise and jitter requirements.

The AD9572 is a fiber channel/Ethernet clock generator IC with 7 clock outputs. The AD9572 uses a fully integrated dual VCO/PLL core, an input crystal or clock frequency of 25 MHz, preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz and 125 MHz, a choice of LVPECL or LVDS output format, integrated loop filters, a copy of the reference clock output, rates configured via strapping pins, 3.3 V operation and a 6 mm × 6 mm, 40-lead LFCSP package.

AD9552 is a frequency upconverter produced by Analog Devices. It converts a low frequency input reference signal to a high frequency output signal. Input frequencies range from 6.6MHz to 112.5MHz, and output frequencies can reach 900MHz. It has preset pin programmable frequency translation ratios, arbitrary frequency translation ratios via SPI port, on-chip VCO, crystal resonator and/or external oscillator as a reference frequency source, secondary output (either integer-related to the primary output or a copy of the reference input), rms jitter: <0.5ps, SPI-compatible, 3-wire programming interface, single supply (3.3V), low power (under most conditions) <400 mW, and small package size (5mm x 5mm). It can effectively replace high frequency VCXO, OCXO and SAW resonators, and provide low jitter extremely flexible frequency translation for SONET/SDH.

The AD9551 multiservice clock generator has the function of translating between any two standard network rates. It supports dual reference inputs and dual clock outputs, and can be programmed for standard network rate translation or arbitrary rational rate translation through pins or SPI. The output frequency range is from 10 MHz to 900 MHz, and the input frequency range is from 19.44 MHz to 806 MHz. It meets the OC-192 high band jitter requirement, supports standard forward error correction (FEC) rates, supports holdover operation, supports hitless switchover and phase build-out (even with unequal reference frequencies), has a SPI-compatible 3-wire programming interface, and operates on a single supply (3.3 V).

This document describes the features and characteristics of the Dual Input Network Clock Generator/Synchronizer AD9549 Rev. D. It features flexible reference inputs, input frequencies ranging from 8 kHz to 750 MHz, two reference inputs, loss of reference indicators, auto and manual holdover modes, auto and manual switchover modes, smooth A-to-B phase transition, excellent stability in holdover mode, programmable 16 + 1-bit input divider and feedback divider, multiple output frequencies, programmable digital loop filter, high speed digitally controlled oscillator (DCO) core, direct digital synthesizer (DDS) with integrated 14-bit DAC, excellent dynamic performance, and software controlled power-down.

AD9548 Rev. B is a Quad/Octal Input Network Clock Generator/Synchronizer from Analog Devices, supports Stratum 2 stability, reference switching and reference switching, supports 1Hz to 750MHz input reference frequency, and output frequency up to 450MHz

This document introduces the AD9540 low jitter clock generator

AD9524 is a low-jitter clock generator with 6 LVPECL/LVDS/HSTL/13 LVCMOS outputs.

The AD9523-1 is a low jitter clock generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS outputs

AD9523 Rev. B is a low jitter clock generator with 14 LVPECL/LVDS/HSTL and 29 LVCMOS outputs. It provides accurate output frequency and start-up frequency accuracy, zero delay operation, and precise input-to-output edge timing. It also features adjustable delay, output-to-output skew, automatic synchronization, and output dividers with jitter-free adjustable delay. The device has a low absolute output jitter and a wide integration range. It is controlled through a serial control port and has a dual PLL architecture.

12 LVDS/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9522-4

AD9522-3 is a 12-channel LVDS/24-channel CMOS output clock generator produced by ADI. It has an integrated 2GHz VCO, supports a frequency range of 1.72-2.25GHz, supports CMOS, LVPECL or LVDS reference signals, and supports 16.62-33.3MHz crystal inputs. It supports optional reference clock doubling, automatic and manual reference switching, automatic recovery and digital or analog lock detection.

AD9515 is a low jitter, low phase noise clock distribution IC that features programmable dividers, coarse delay adjustment and 1.6 GHz LVPECL, 800 MHz/250 MHz LVDS/CMOS clock outputs. It can provide low jitter and low phase noise clock signals to high performance ADC, DAC, DDS, DDC, DUC and MxFE applications.