CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
The document describes the CD4071B (Quad 2-Input OR Gate), CD4072B (Dual 4-Input OR Gate), and CD4075B (Triple 3-Input OR Gate). These devices provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.
| Product Function | positive-logic OR function |
|---|---|
| Package Drawing (CD4071BM96) | SOIC D |
| Package Drawing (CD4071BNSR) | SO NS |
| Package Drawing (CD4071BPWR) | TSSOP PW |
| Reel Diameter (SOIC/SO NS) | 330.0 mm |
| Reel Width (SOIC/SO NS) | 16.4 mm |
| Reel Width (TSSOP) | 12.4 mm |
| Pack Length | 346.0 mm |
| Pack Width | 346.0 mm |
| Pack Height (TSSOP) | 29.0 mm |
These devices provide direct implementation of the positive-logic OR function.
All listed package types contain 14 pins.
The maximum peak temperature is 260C.