Guide describing the features, architecture, registers, and operation of the KeyStone UART peripheral.
The KeyStone UART peripheral provides serial‑to‑parallel and parallel‑to‑serial conversion, supporting up to 16‑byte FIFOs for both transmit and receive. It includes a programmable baud‑rate generator, interrupt handling, DMA support, and power‑management features.
The manual covers functional block diagrams, clock generation, signal descriptions, register maps, FIFO modes, autoflow control, loopback, reset considerations, and emulation details, helping developers integrate and configure the UART in KeyStone‑based systems.
| FIFO depth | 16 bytes |
|---|---|
| Baud‑rate divisor range | 1 to 65535 |
| Oversampling modes | 16× or 13× |
The UART’s transmit and receive FIFOs can each store up to 16 bytes.
Divisors from 1 to 65535 are supported.
The UART can operate with either 16× or 13× oversampling.