This user guide describes the features and behavior of the ALTERA_PLL megafunction that you can configure through the parameter editor in the Quartus® II software.
This document serves as a user guide for the ALTERA_PLL megafunction, which allows users to configure phase-locked loop (PLL) circuitry within the Quartus II software environment. It assumes familiarity with megafunctions and the MegaWizard Plug-In Manager, directing new users to the Megafunction Overview User Guide for background information. The guide details how the ALTERA_PLL instantiates a generic PLL to support migration between architectures and offers placement flexibility across different device types.
| Supported Device Family | Stratix V |
|---|---|
| Maximum Clock Outputs | 18 |
| Reference Clock Frequency Default | 100.0 MHz |
| Number of Clocks Range | 1 to 18 |
| Duty Cycle Range | 1 to 99 |
The supported modes are direct, external feedback, normal, source synchronous, and zero delay buffer mode.
It supports the Stratix V device family.
The default value for the reference clock frequency is 100.0 MHz.