This user guide describes the Altera 40- and 100-Gbps Ethernet MAC and PHY MegaCore functions that are available for use in building Altera 100-Gbps Ethernet devices.
This document describes the Altera 40- and 100-Gbps Ethernet (40GbE and 100GbE) MAC and PHY MegaCore functions which implement the IEEE 802.3ba 40G and 100G Ethernet Standard. The product provides an interface composed of a single, packet-based channel that is logically compatible with previous generation Ethernet systems, supporting either four or twenty 64b/66b encoded and scrambled virtual lane streams.
| Standard Compliance | IEEE 802.3ba-2010 Higher Speed Ethernet Standard |
|---|---|
| Interface Speed | 10.3125 Gbps per lane |
| Max Receive Frame Length | 9600 bytes |
The core offers preliminary support for Stratix IV GT I1 or C2 speed grade and Stratix V GX I2, I3, or C2 speed grade.
Yes, the IP core offers Transmit (TX) only configuration options and Receive (RX) only configuration options.
The core supports Avalon Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interfaces, as well as optional custom streaming interfaces.