Altera SCFIFO and DCFIFO Megafunctions User Guide

About this manual

This document serves as a user guide for Altera's SCFIFO (single-clock FIFO) and DCFIFO (dual-clock FIFO) megafunctions. These parameterizable functions are designed for data buffering applications that comply with first-in-first-out data flow in synchronous or asynchronous clock domains. The guide details the specific megafunction names, including DCFIFO_MIXED_WIDTHS, and explains that the term DCFIFO refers to both the standard and mixed-width versions unless specified otherwise.

What's inside

• Configuration Methods
• Specifications
• Parameter Specifications
• Functional Timing Requirements
• Output Status Flags and Latency
• Metastability Protection and Related Options
• Synchronous Clear and Asynchronous Clear Effect
• Different Input and Output Width
• Constraint Settings
• Coding Example for Manual Instantiation

Specifications

Frequently asked questions

When should you use manual instantiation?

Manual instantiation should only be used by expert users who know the detailed specifications of the megafunctions and can ensure valid input/output ports and parameter values.

What are the two methods for configuring and building the FIFO megafunctions?

You can configure them using the FIFO parameter editor in the Quartus II software, or by manually instantiating the megafunctions if you are an expert user.

What clock signal is required for the SCFIFO block?

The SCFIFO block requires a positive-edge-triggered clock signal.

Which clock signals are used to synchronize the read and write signals in the DCFIFO block?

The read and write signals in the DCFIFO block are synchronized to the rdclk and wrclk clocks, respectively.