This file is the user guide of DDR and DDR2 SDRAM controllers of Altera Corporation
This document serves as the user guide for the Altera DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP, part of the External Memory Interface Handbook Volume 3. It details the integration of the ALTMEMPHY megafunction with high-performance memory controllers to provide simplified interfaces for industry-standard DDR and DDR2 SDRAM devices. The guide supports full-rate or half-rate interfaces and includes the high-performance controller II (HPC II) architecture.
| Supported Device Families | Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, Stratix II GX, Stratix III, Stratix IV |
|---|---|
| Interface Types | Full-rate or half-rate DDR and DDR2 SDRAM interfaces |
| Controller Architecture | High-performance controller II (HPC II) |
| Software Compatibility | Altera Complete Design Suite version 11.0 |
The ALTMEMPHY megafunction acts as an interface between a memory controller and the memory devices, performing read and write operations.
Yes, you may share some of the PLL clock outputs between multiple instances, but you cannot share a PLL between multiple instances of the ALTMEMPHY megafunction.
Final support means the core is verified with final timing models and meets all functional and timing requirements for the device family.