Altera Embedded Peripherals IP User Guide

About this manual

The Embedded Peripherals IP User Guide from Altera (UG-01085-11.0, June 2011) documents embedded peripheral IP cores for Altera designs. It was updated for Altera Complete Design Suite version 11.0 and includes sections for off-chip interface peripherals, on-chip storage peripherals, and transport and communication.

The table of contents lists cores such as the SDRAM Controller, CompactFlash, Common Flash Interface Controller, EPCS Serial Flash Controller, JTAG UART, UART, SPI, Optrex 16207 LCD Controller, PIO, PCI Lite, and On-Chip FIFO Memory. Individual chapters describe functional descriptions, configuration settings, software programming models, register maps, and document revision histories.

What's inside

• Introduction
• SDRAM Controller Core
• CompactFlash Core
• JTAG UART Core
• UART Core
• SPI Core
• PIO Core
• PCI Lite Core
• On-Chip FIFO Memory Core
• Avalon Streaming Channel Multiplexer and Demultiplexer Cores

Frequently asked questions

What Altera Complete Design Suite version is this guide updated for?

It is updated for Altera Complete Design Suite version 11.0.

What is the publication date of this user guide?

The document publication date is June 2011.

What document number identifies this guide?

The guide is identified as UG-01085-11.0.

What main sections organize the documented peripherals?

The guide is organized into Off-Chip Interface Peripherals, On-Chip Storage Peripherals, and Transport and Communication sections.