Altera Corporation's FPGA series product user manual released in 2012, which introduces the features and behavior of the ALTPLL_RECONFIG megafunction, and how to configure it in the Quartus II software through the parameter editor.
This user guide describes the features and behavior of the ALTPLL_RECONFIG megafunction, which facilitates dynamic real-time reconfiguration of Phase-Locked Loops (PLLs) in Altera devices. The megafunction allows users to update output clock frequency, PLL bandwidth, and phase shifts without reconfiguring the entire FPGA. It supports reconfiguration of pre-scale, feedback, and post-scale counter parameters, as well as delay elements or phase shifts.
It implements logic to facilitate dynamic real-time reconfiguration of Phase-Locked Loops (PLLs) in Altera devices.
Users can update the output clock frequency, PLL bandwidth, and phase shifts without reconfiguring the entire FPGA.
The megafunction supports reconfiguration from Memory Initialization File (.mif) and Hexadecimal File (.hex).