This application note outlines the necessary steps to ensure the STR91xFA is configured for optimum performance for those applications which require the STR91xFA to operate at full speed and deliver the highest performance from the CPU core and highest bandwidth of data movement.
This document provides guidelines for configuring the STR91xFA series of Flash MCUs to achieve maximum performance. It details the initialization of system configuration registers to optimize the ARM966E CPU core, which operates at up to 96 MHz. Key areas covered include system clock configuration using the PLL, managing wait states for Flash and SRAM access, and utilizing buffered writes.
| CPU Core | ARM966E RISC processor core |
|---|---|
| Max CPU Frequency | 96 MHz |
| Flash Memory | 544 Kbytes |
| SRAM | 96 Kbyte |
| Max APB Peripheral Clock | 48 MHz |
Update the PLL configuration register (SCU_PLLCONF) to boost the system clock to 96 MHz using the appropriate multiplier and divider.
The STR91xFA should be used in ARM (32-bit) mode for applications needing best performance.