This application note is intended for system designers who require a software and hardware implementation overview of the low-power modes of the STM32F101xx, STM32F102xx and STM32F103xx products. It describes how to use the STM32F10xxx product family and details the clock systems, register settings and low-power management in order to optimize the use of STM32F10xxx in applications where low power is key.
This application note provides a software and hardware implementation overview of the low-power modes available in the STM32F101xx, STM32F102xx, and STM32F103xx product families. It details clock systems, register settings, and low-power management techniques to optimize power consumption in applications where low power is a key requirement. The document explains how to use the three main low-power modes: Sleep, Stop, and Standby, as well as techniques for reducing power in Run mode by slowing down system clocks and gating peripheral clocks.
| Operating voltage supply | 2.0 V to 3.6 V |
|---|---|
| Internal digital power | 1.8 V |
| Low-speed internal RC frequency | 40 kHz |
In Standby mode, the regulator is powered off, and the contents of registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.
The device requires a 2.0 V to 3.6 V operating voltage supply (Vpp).
The contents of the registers and SRAM are lost except for those concerned with the Standby circuitry and the Backup domain.
The LSI RC frequency changed from 32 kHz to 40 kHz.