This document provides a hardware implementation overview of the low power modes of the STR75x product family, and details the components of supply circuitry, clock systems, register settings, and low power management in order to optimize the use of STR750 in applications where low power is key.
This document provides a hardware implementation overview of the low power modes available in the STR75x product family. It details the components of supply circuitry, clock systems, and register settings required to optimize power consumption.
The note covers four specific power supply schemes, ranging from single external voltage sources to dual voltage configurations. It explains the operation of the Main and Low Power voltage regulators, including their startup monitors, and describes specific low power modes such as SLOW, PCG, WFI, STOP, and STANDBY.
| VDD_IO Supply Range | 3.3V ±0.3V or 5V ±0.5V |
|---|---|
| V18 Digital Power Supply | 1.8V ± 0.15V |
| Low Power Regulator Output | 1.6V ± 0.2V |
| Low Power Regulator Output (Approx) | approximately 1.4V |
| Main Regulator Static Consumption | ~100µA typical |
The device supports four schemes: single external 3.3V, dual external 3.3V and 1.8V, single external 5.0V, and dual external 5.0V and 1.8V.
No, STANDBY mode is not available in Power Scheme 2.