This document describes how to use the DMA controller of STM32F101xx and STM32F103xx, including the main features of DMA and performance analysis. It also provides programming examples of using the DMA controller, including obtaining ADC continuous sampling data using SPI transmission and achieving fast data transfer with GPIO using DMA.
This application note describes how to use the Direct Memory Access (DMA) controller on STM32F101xx and STM32F103xx microcontrollers. It explains how the DMA controller, Cortex-M3 core, and AMBA bus architecture enable high data bandwidth and low-latency software development. The document also details how to fully utilize these features and ensure correct response times for different peripherals and subsystems.
The note covers the main characteristics of the DMA controller, including its seven channels, hardware and software priority settings, and support for various data transfer modes. It provides a performance analysis of the polling priority scheme, multi-level bus structures, and data bus bandwidth limitations. Finally, it includes programming examples for using DMA with SPI and ADC peripherals. This manual is written in Chinese.
| Number of DMA Channels | 7 channels (Channel 1 to 7) |
|---|---|
| Supported Transfer Modes | Memory-to-Memory, Memory-to-Peripheral, Peripheral-to-Memory, Peripheral-to-Peripheral |
| Maximum Data Words per Transfer | 65536 data words |
| Bus Arbitration Time | 1 AHB clock cycle |
| Peripheral Access Time | 1 AHB clock cycle + 2 APB clock cycles + 1 AHB clock cycle |
| SRAM Read/Write Time | 1 AHB clock cycle (single operation) or 2 AHB clock cycles (read then write) |
This application note covers the STM32F101xx and STM32F103xx series microcontrollers.
There are 7 DMA channels available, numbered from Channel 1 to Channel 7.
The DMA controller can transfer up to 65536 data words.
Yes, it supports Peripheral-to-Peripheral data transfer in addition to memory-based transfers.