This application note provides information on how to use and take full advantage of the STR91xFA DMA controller. It describes the most typical and useful control scenarios for each peripheral DMA transfer. Software is available for download from www.st.com.
This document provides information on using the STR91xFA DMA controller (DMAC). It describes how to utilize the controller to transfer data between memory and peripherals without CPU intervention, thereby improving system speed. The note covers typical control scenarios and useful configurations for DMA transfers.
| Number of DMA channels | Eight |
|---|---|
| DMA channel priority | Channel 0 highest, Channel 7 lowest |
| Number of DMA request lines | 14 |
| Maximum data per block | 256 |
| Data width configuration | Byte, half-word or word |
It allows devices to transfer data to or from the system's memory and registers without the intervention of the CPU.
It prevents the STR9 core from being overloaded by serving all peripherals, resulting in an overall speed-up in CPU operation.
The DMAC supports memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers.