STMicroelectronics AN2548 Application Note Using the STM32F101xx and STM32F103xx DMA Controller

About this manual

This document details the Direct Memory Access (DMA) controller found in the STM32F101xx and STM32F103xx series of microcontrollers. It explains how the DMA controller utilizes the Cortex-M3 core and AMBA bus architecture to provide high data bandwidth and low latency response times for software development.

What's inside

• Introduction
• DMA controller description
• Main features
• Performance considerations
• Round robin priority scheme
• Multi-layer structure and bus stealing
• DMA latency
• Choosing channel priority
• DMA programming examples

Specifications

Frequently asked questions

What is the maximum bus system latency for the first data seen from the CPU?

The maximum bus system latency for the first data, seen from the CPU, is of one bus cycle (maximum two APB clock cycles).

How does the STM32F10xxx DMA handle data transfers compared to burst mode?

The STM32F10xxx DMA uses a single bus cycle for data transfers using a 'bus stealing' mechanism, which minimizes CPU stalling time.