This document describes the definition and design of self-tests for SPC564Ax devices, with a focus on self-tests for the CPU subsystem, digital peripherals, and analog peripherals.
This document provides guidance on developing self-tests for SPC564Ax devices, which are designed for powertrain applications such as engine and transmission control. It addresses the need to conform to safety standards like IEC 61508 or ISO 26262 by detailing self-test capabilities for various components.
The note is structured to cover self-tests for the CPU subsystem, digital peripherals, and analog peripherals. It explains the distinction between power-on self-tests for latent fault detection and run-time self-tests for single point of failure detection. Specific sections detail the implementation of tests for the CRC unit, DMA controller, Flash, RAM, and various peripheral modules.
SPC564Ax devices have been designed for Powertrain applications like engine control and transmission.
Self tests can be used at power on or during run time.
Power on self tests focus on latent fault detection and usually cover all modules of a given microcontroller.