This application note details the steps required to properly initialize the SPC564Bxx and SPC56ECxx from reset as well as how to control the second core.
The document is an application note titled AN3995, serving as a getting started tutorial for the SPC564Bxx and SPC56ECxx families of Power Architecture-based microcontrollers. These devices feature a dual-core architecture combining an e200z4d core and an e200z0h core, targeting automotive body and gateway applications.
The note details the necessary steps to properly initialize the device from reset and control the second core (e200z0h). It covers boot mechanisms, memory partitioning strategies for dual-core operations, MMU configuration, clock setup, cache management, and provides example C code. The guide is intended to be read alongside the SPC564Bxx and SPC56ECxx Reference Manual.
| Internal Flash memory | up to 3 MB |
|---|---|
| Internal SRAM memory | up to 256 KB |
| Operating speed | up to 120 MHz |
The primary core is an e200z4d.
The available modes are Flash Boot (Default), Serial Boot via LINFlex, and Serial Boot via FlexCAN.