This document is a technical note on using Analog Devices' DSP components and development tools. It provides information on the minimum rise time specifications for the ADSP-2105, as well as the cause and solution for a customer's issue with the serial ports.
This Engineer-to-Engineer Note (EE-71) addresses issues where faster silicon revisions of the ADSP-2105 caused serial ports to stop working due to glitches and rise times on the SCLK signal. The document explains why a minimum rise time specification is critical for signals such as interrupts and clocks to prevent glitches from overcoming input buffer hysteresis.
| Recommended minimum risetime for critical input clock signals | 0.5 V/ns |
|---|---|
| Maximum glitch width rejected by input buffers | about 1ns |
Analog Devices recommends ensuring all critical input clock signals have minimum risetimes of 0.5 V/ns.
Signals such as Serial Port clocks (SCLK & RFS) or hardware interrupts (/ IRQx) are the most problematic because they cannot glitch at any time.