This document serves as an Engineer-to-Engineer Note regarding the Analog Devices ADSP-21160 DSP. It specifically examines the backward compatibility of the ADSP-21160's six 8-bit wide link ports with previous SHARC DSPs, particularly the ADSP-2106x series. The text details the general operation of the link ports, including their bi-directional data transfer capabilities, handshaking mechanisms, and maximum transfer rates up to 80 MHz.
The document provides technical details on configuring the link ports for compatibility with older ADSP-2106x devices, noting that while they are logically compatible, electrical compatibility requires specific voltage considerations. It includes tables comparing clock frequencies and skew calculations for receiver-side transfers between the ADSP-21160 and ADSP-21062L. Furthermore, the note offers core-driven and DMA-driven transfer examples with code listings to assist developers in implementing these connections.
| Number of link ports | six 8-bit wide link ports |
|---|---|
| Data lines | eight data lines (LxDAT7-0) |
| Maximum transfer rate | 80 MHz |
| Transmission line impedance | 50 Ohm or greater |
Yes, they are logically compatible, though only an ADSP-2106xL is electrically compatible without a voltage conversion stage.
The SYSCON, LCOM, LAR, and LCTLx registers control the link ports operating modes for the I/O processor.