describes the precautions for using serial ports in ADSP-21xx, including the startup timing, frame synchronization, data bit number and other issues to note when using serial ports
This Engineering Note addresses specific startup issues encountered when using the ADSP-21xx Serial Port (SPORT) in unframed or frameless modes. Users reported that the first one or two bits of a data stream were being lost during initialization. The document explains that this is a side effect of the hardware design, where the SPORT takes two SCLK cycles to enable and looks for a frame sync on the third cycle. In frameless modes, if the clock is only active when data is present, the port may skip initial data bits because it interprets the continuous frame signal as valid data cycles.
The SPORT takes two SCLK cycles to enable and looks for a frame sync on the third cycle; if the clock is only active when data is present, it skips the initial bits.
Users can generate two initial dummy bits on the data stream or de-assert the frame signal for 2 or more SCLK cycles before asserting it when data starts.